The present invention is related to field programmable integrated circuits, especially Field Programmable Gate Arrays (FPGAs), and more particularly, to floating gate MOS transistors used as switching elements in a field programmable gate array FPGA.
An FPGA cell is a combination of circuit elements which act as a single nonvolatile switch. Its function is to electrically connect or isolate two nodes in the FPGA circuit array.
Typically, an FPGA has an array of logic elements and wiring interconnections with thousands, or even tens of thousands, of programmable interconnects so that the FPGA can be configured by the user into an integrated circuit with defined functions. Each programmable interconnect, or switch, can connect two circuit nodes in the integrated circuit to make (or break) a wiring interconnection or to set the function or functions of a logic element.
FPGAs use either memory cells or antifuses for the programmable interconnect. Memory cells are reprogrammable and antifuses are programmable only once. A new non-volatile memory-type of programmable interconnect is disclosed in a patent application, U.S. application Ser. No. 08/754,116, entitled, "A GENERAL PURPOSE, NON-VOLATILE REPROGRAMMABLE SWITCH," filed Nov. 21, 1996 by Robert J. Lipp, Richard D. Freeman, Robert U. Broze, John M. Caywood, and Joseph G. Nolan, III, and assigned to the present assignee. In the FPGA described in the patent application, a non-volatile reprogrammable transistor memory (NVM) cell is used to provide a general purpose switching element to randomly interconnect FPGA wiring and circuit elements. Basically an NVM cell has an MOS transistor with a floating gate which may be charged and/or discharged. Charging and/or discharging the floating gate provides for the non-volatile programmability feature of NVM technologies.
In an FPGA, indeed, in any integrated circuit, it is important that the elements of the FPGA be as compact as possible for an efficient layout of the circuit and be as easily manufactured as possible. Robert U. Broze, U.S. Pat. No. 5,633,518 issued May 27, 1997 for "Non-Volatile Reprogrammable Interconnect Cell with FN Tunneling and Programming" and assigned to the present assignee is directed toward highly compact cells of one of the programmable interconnects described in patent application Ser. No. 08/754,116, supra. An efficient array of such interconnects, each of which is selectively programmable, is achieved. Each programmable interconnect cell has a first MOS transistor having first and second source/drains connected to first and second circuit nodes respectively, and a floating gate for turning the first MOS transistor off and on at a threshold responsive to the amount of charge on the gate. The cell also has a tunneling device with one terminal connected to the floating gate of the first MOS transistor and coupled to a programming/erase line through a tunneling oxide layer, a control gate capacitively coupled to the floating gate, and at least one tunneling control line for controllably inhibiting tunneling through the oxide layer. The tunneling control line and the programming/erase line form a PN junction which is close to, but laterally displaced from, the region below the tunneling oxide layer. Under a reverse bias, the charge depletion region of the junction extends through the region below the tunneling oxide to block tunneling. This permits each programmable interconnect to be selectively programmable.
Co-pending applications Ser. No. 08/708,074 filed Aug. 9, 1996 and Ser. No. 08/704,853 filed Aug. 27, 1996 disclose FPGA cells having an EPROM split gate sense transistor, a switch transistor and a Fowler-Nordheim (FN) tunnelling device, all having interconnected floating gates. Programming of the cell is by hot electron injection of electrons to the floating gate in the EPROM transistor, and erase of the cell is by electron tunneling from the floating gate in the FN device. Thus, the switch transistor is programmed off by hot injection of electrons to the floating gate in the EPROM device, and the switch transistor is erased on by tunneling of electrons from the floating gate in the FN device.